Teach with Past the Magic

Each activity, example, Reference, prediction, diagnosis, and construction link below opens the LC-3 instrument on the named starting state. Paste them into a syllabus, a lab handout, or a slide. Everything runs in the browser — students need no account and no setup.

Built for students and instructors using Patt & Patel's Introduction to Computing Systems, third edition.

Recommended sequence

From tracing a control decision to building ADD

Trace one control decision, then predict, diagnose, and construct the ADD result state.

Go to Follow one instruction
Go to ADD (register mode)
Go to ADD result never reaches its register
Go to Build an ADD result clock

Guided activities

Work through a narrated machine or C-runtime sequence.

Follow one instruction

Area: LC-3 instruction execution
Concept: Fetch, decode, and execute
Kind: activity
Outcome: Step the first LD through fetch, decode, and execute, then identify its R1 write and P condition code.
Prerequisites: None
Duration: about 90 seconds

Your first LC-3 program

Area: LC-3 assembly programming
Concept: Assemble, run, edit, and rerun
Kind: activity
Outcome: Assemble and run the program that prints A, change its stored character to B, then reassemble and observe the new output.
Prerequisites: None
Duration: about a minute

Numbers: one word, four readings

Area: Data representation
Concept: 16-bit readings and signed overflow
Kind: activity
Outcome: Predict and step x7FFF plus one, then report the resulting word, its signed reading, and the N condition code.
Prerequisites: None
Duration: about two minutes

Pointer swap: follow the storage

Area: C programs and runtime storage
Concept: Pointer aliasing across stack frames
Kind: activity
Outcome: Compile and line-step the swap call, using Stack and Objects to follow both pointer targets and the two caller-object writes.
Prerequisites: None
Duration: about three minutes

Recursive frames: descend and unwind

Area: C programs and runtime storage
Concept: Recursive activation records
Kind: activity
Outcome: Line-step factorial through three live recursive frames, the base-case return, one unwind, and the final 6! = 720 output.
Prerequisites: None
Duration: about four minutes

Linked-list lifecycle

Area: C dynamic memory and linked structures
Concept: Allocation, links, traversal, and cleanup
Kind: activity
Outcome: Line-step the list through allocation, insertion, one traversal hop, safe head removal, and cleanup with no allocated blocks left.
Prerequisites: None
Duration: about five minutes

LDR: from bits to a register

Area

LC-3 circuit execution

Concept

Memory readiness and LDR dataflow

Kind

activity

Outcome

Trace one real LDR clock by clock through fetch, both access checks, two five-clock memory reads, effective-address formation, and witnessed register/condition-code writeback.

Prerequisites

Follow one instruction (activity:follow-one-instruction)

Duration

about five minutes

Predict exercises

Commit before reveal, then compare the real control decision.

ADD (register mode)

Area

LC-3 microarchitecture

Concept

ADD result-state controls

Kind

predict

Outcome

Commit the destination loads, bus driver, and next state for the register-mode ADD result clock, then compare the reveal.

Prerequisites

Follow one instruction (activity:follow-one-instruction)

AND (immediate mode)

Area: LC-3 microarchitecture
Concept: Immediate-mode ALU selects
Kind: predict
Outcome: Commit the select fields for the shipped immediate-mode AND clock, then compare the reveal.
Prerequisites: None

BR, not taken

Area: LC-3 microarchitecture
Concept: BEN-controlled next state
Kind: predict
Outcome: Commit the next state for a BRz when the preceding instruction leaves the positive condition set, then compare the reveal.
Prerequisites: None

BR, taken

Area: LC-3 microarchitecture
Concept: BEN-controlled next state
Kind: predict
Outcome: Commit the next state for a BRz when the preceding instruction leaves the zero condition set, then compare the reveal.
Prerequisites: None

LD (PC-relative)

Area: LC-3 microarchitecture
Concept: PC-relative load addressing
Kind: predict
Outcome: Commit the loads, bus driver, and next state at the shipped PC-relative LD clock, then compare the reveal.
Prerequisites: None

LDR: read a next link

Area: LC-3 microarchitecture
Concept: Base-plus-offset load addressing
Kind: predict
Outcome: Commit the loads, bus driver, selects, and next state while LDR forms the address of a node next link, then compare the reveal.
Prerequisites: None

LEA does not set the condition codes

Area: LC-3 microarchitecture
Concept: Address generation without a condition-code write
Kind: predict
Outcome: Commit the load signals for the shipped LEA clock, then compare the reveal that preserves the condition codes.
Prerequisites: None

ST (PC-relative)

Area: LC-3 microarchitecture
Concept: Memory-write control
Kind: predict
Outcome: Commit the memory action and next state for the shipped PC-relative ST clock, then compare the reveal.
Prerequisites: None

LDI: the indirection pivot

Area: LC-3 microarchitecture
Concept: Indirect-address transfer
Kind: predict
Outcome: Commit the loads, bus driver, and next state at the LDI indirection pivot, then compare the reveal.
Prerequisites: None

TRAP: saving state before the jump

Area: LC-3 microarchitecture
Concept: Saving state during TRAP entry
Kind: predict
Outcome: Commit the bus driver and loads for the shipped TRAP x25 entry clock, then compare the reveal.
Prerequisites: None

An illegal opcode forces a system entry

Area: LC-3 microarchitecture
Concept: Illegal-opcode exception entry
Kind: predict
Outcome: Commit the bus driver and next state at the illegal-opcode entry clock, then compare the user-mode branch reveal.
Prerequisites: None

Diagnose control words

Identify and repair a fault from its architectural consequence.

ADD result never reaches its register

Area

LC-3 microarchitecture

Concept

ADD destination-register load

Kind

diagnose

Outcome

Repair the single editable control field so the ADD result reaches its destination and both grader cases pass.

Prerequisites

ADD (register mode) (predict:operate-add)

A taken branch falls through

Area: LC-3 microarchitecture
Concept: Conditional branch sequencing
Kind: diagnose
Outcome: Repair the next-state condition so BRp takes and falls through in the two seeded condition-code cases.
Prerequisites: None

LDR ignores its signed offset

Area: LC-3 microarchitecture
Concept: Signed offset address generation
Kind: diagnose
Outcome: Repair the address-adder input so positive and negative LDR offsets move MAR from BaseR and both grader cases pass.
Prerequisites: None

LDI skips its second access check

Area: LC-3 microarchitecture
Concept: Access checking after indirection
Kind: diagnose
Outcome: Repair the access-check load so protected and safe indirect targets produce the expected ACV result.
Prerequisites: None

LDI completes a read but drops its value

Area: LC-3 microarchitecture
Concept: Memory-ready data capture
Kind: diagnose
Outcome: Repair the memory-data load so MDR captures the indirect pointer after both one-clock and five-clock reads.
Prerequisites: None

Illegal-opcode entry selects the wrong table

Area: LC-3 microarchitecture
Concept: Exception table selection
Kind: diagnose
Outcome: Repair the table load so user- and supervisor-mode illegal-opcode entries record the exception table and take the expected path.
Prerequisites: None

Construct control words

Author a control word and check it on two deterministic starts.

Build an ADD result clock

Area

LC-3 microarchitecture

Concept

Authoring an ADD result state

Kind

construct

Outcome

Build the control word that writes register- and immediate-mode ADD results, updates NZP, and passes both grader cases.

Prerequisites

ADD result never reaches its register (diagnose:add-missing-register-load)

Build a memory-write wait state

Area: LC-3 microarchitecture
Concept: Authoring a memory-write wait state
Kind: construct
Outcome: Build the state-16 control word that keeps writing until ready and passes one-clock and five-clock memory cases.
Prerequisites: None

Build the BEN-controlled branch

Area: LC-3 microarchitecture
Concept: Authoring BEN-controlled sequencing
Kind: construct
Outcome: Build the branch next-state rule that distinguishes the seeded taken and not-taken BRp cases.
Prerequisites: None

Build TRAP vector and privilege completion

Area: LC-3 microarchitecture
Concept: Authoring TRAP entry completion
Kind: construct
Outcome: Build the state-47 control word that latches the TRAP vector, enters supervisor mode, and preserves the old-mode branch in both cases.
Prerequisites: None

Open the gate-level bridge

Open the instrument and choose the Gates rung. Inspect SR2MUX, the PC register, a memory cell, and GatePC as one of sixteen parallel one-bit slices, with the element's static relation beside evidence from the selected real machine clock.

Examples

Linked list

Build, insert, traverse, delete, and completely free a checked three-node linked list.

Matrix multiply

Multiply two small matrices and inspect the row-major result as a live grid.

Input calculator

Read two integers and an operator with scanf, then follow the selected switch arm.

Stack calculator

Evaluate one-digit expressions with ASCII conversion, an operand stack, and assembly subroutines.

LC-3 reference

LC-3 instructions

Open the 15 opcodes, accepted forms and aliases, effects, and condition-code behavior.

LC-3 useful tables

Open TRAP routines, mapped registers, number forms, powers of two, and character codes.

Embed the instrument

Paste this iframe into a course page. Share still offers a manual-copy URL when clipboard permission is denied.

<iframe src="https://www.pastthemagic.com/lc3?embed" title="Past the Magic LC-3" loading="lazy" allow="clipboard-write"></iframe>

Make your own moment links

A reproducible instruction-boundary moment can be a link after at least one completed instruction. Share refuses states a clean replay cannot reproduce: typed input, memory edits, memory-latency changes during execution, a raw .obj load, a partly completed instruction, or a run at or above 50,000 instructions. When available, the copied link captures the program, where you are standing, the view, the memory latency, and the exact position in the run. A student who opens it lands on the moment you mean, not a blank editor. The program travels inside the URL itself, so links need no account and no server-side storage.

Piloting this fall?

If you are using Past the Magic in a course, I would like to hear about it — what you assigned, what landed, what did not. teach@pastthemagic.com